invention relates to I/O processors, and more particularly, to a method for synchronizing the pulse input values of a master controller to either of a primary and secondary redundant pair of I/O processors.
Process Control Systems with backup process controllers such as described and claimed in U.S. Pat. No. 4,133,027, issued to J. A. Hogan on Jan. 2, 1979, and U.S. Pat. No. 4,141,066, issued to Y. Keiles on Feb. 20, 1979, include a backup controller having a dedicated Random Access Memory (RAM) and a dedicated Read-Only Memory (ROM). The backup controller is essentially idle or can be doing some background tasks, but not tasks relating directly to the process control function. Upon detection of a failure of one of the primary process controllers, the data stored in the RAM of the failed controller must be transferred to the RAM of the backup controller to perform the operations of the primary controller. These systems describe a 1:N redundancy system.
Existing systems, such as that described in U.S. patent application, Ser. No. 07/299,859, U.S. Pat. No. 4,958,270 filed on Jan. 23, 1989, and assigned to Honeywell Inc., the assignee of the present application, provide for a 1:1 redundancy system, whereby the data base of a secondary device (i.e., secondary or backup controller) is updated periodically such that the updating process is transparent to the primary functions and does not tie-up (or penalize) CPU or processor performance and utilizes a minimum amount of time. When a failover condition occurs, there is a period of time when no communications can take place (i.e., an outage) between the primary controller and the remainder of the system. Further, the primary and secondary controllers are in a predefined location, and the software utilized for implementing this redundancy feature (i.e., redundancy software) is not transparent to other layers of software above the redundancy software. For example, if a Universal Station of a plant control network were to interrogate a controller (i.e., a primary controller since the secondary controller cannot be interrogated), of a process controller of a process control system, for a value, during failover the controller is unable to respond and the universal station outputs question marks on the display to the operator.
The present invention provides a method for synchronizing the pulse input values accumulated in a primary and secondary pulse input I/O processors (IOP) of a 1:1 redundant pair of I/O processors to the value in a master controller. The system in which the present invention can be found precludes the initiation of communications between the primary and secondary IOP on a communication network. Each IOP includes pulse accumulation hardware which is separate and distinct in each IOP, although the high speed pulse input is coupled to both the primary and secondary IOPs. The present invention relates to the method in which the pulse input values of the primary and secondary IOPs can be synchronized to the master controller such that upon a failure of the primary IOP, a master controller can continue predefined totalizing functions using the accumulated pulse inputs values from the secondary IOP. The present invention finds advantage over present day systems in that the type of I/O, i.e., redundant high speed pulse input accumulation, is not satisfied in present day process control systems. In the present invention, the master controller is configured to interface with the high speed pulse accumulator input devices (the IOPs) such that the input accumulation is performed in the IOP and more refined totalizer functions are performed in the master controller.